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Volume 11 (Oct 22, 2003)

Introduction of VLSI Symposia Presentation Papers (1/2)

The 2003 VLSI (Very Large-Scale Integration) Symposia, an influential international semiconductor conference, was held on June 10-14, 2003, in Kyoto, Japan. Here we will introduce the research results presented by NEC Electronics at the VLSI Symposia.

What is the VLSI Symposia?

The VLSI Symposia is a large conference comparable in size to the International Solid-State Circuits Conference (ISSCC) and the International Electron Devices Meeting (IEDM) that provides a venue for presenting research and development results in the field of semiconductors. The VLSI Symposia, which serves as a forum for presenting new technological developments related to semiconductors, was established in 1981 and has recently become an annual event held every other year in Hawaii and Kyoto.

In recent years, there has been an increase in the number of paper submissions, not only from companies but also universities, graduate schools and research organizations. There also has been a sharp rise in the number of presentations made by researchers from South Korea, Taiwan and other Asian countries. This trend certainly was apparent at this year's symposia approximately 32% of the 161 presentation papers were from Asia, compared with only 15% in 2002.

The VLSI Symposia has two sections: the Technology Symposium, at which materials, LSI manufacturing methods, and so forth are discussed; and the Circuit Symposium, at which circuit architecture is discussed. At this year's Circuit Symposium, the majority of the presentations were related to the latest topical technologies, including memory products, CPUs and wireless communications devices.

NEC Electronics' presentation papers

This year, NEC Electronics presented the following three papers at the two sections of the VLSI Symposia.

<<Paper Titles>>

<<Paper Content>>

Technology Symposium

Accurate Modeling Method for Deep Sub-Micron Cu Interconnect

The copper interconnect cross-section modeling is a method that makes it possible to design copper wiring, which is indispensable to beyond 90nm-class products, through the utilization of high-precision simulations. By combining the process characteristics that depend on the circuit pattern with the copper wiring, circuit formation conditions such as wiring thickness can be accurately determined.

In the past, copper wiring was more susceptible than aluminum wiring to the occurrence of distortion in interconnect cross-sections when fabricating circuits on wafers. And since distortion of 10% or higher was expected, chip area and power consumption had to be increased when designing circuits to make up for this. By employing this newly developed modeling method, however, it is no longer necessary to take distortion into consideration when designing circuits, and therefore chip size and power consumption can be optimized (Figure 1).

While in the past only fixed numerical values for interconnect resistance could be employed in simulations, this new method enables a better understanding of interconnect resistance values, which differ depending on wiring density, spacing between wires, etc. by section, and also makes it possible to accurately determine interconnect resistance and capacity. As a result, the task of verifying the timing of electrical signals, which is essential to circuit design, becomes simplified, the development period is shortened and process ability can be optimized (Figure 2).

NEC Electronics intends to put this new method into practical use starting with the mass production of an LSI utilizing the 90nm process, which is slated for sometime during fiscal year 2003. Development software using this technology is already on the market after having been added to the Synopsys® Star-RCXT™ and Sequence Design Columbus® extraction tools as a new function.

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