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Volume 6 (Aug 25, 2003)

Facing the Challenge of CB-90 Development (1/2)

Part 2: Design Development

The launch of the CB-90 Development Conference

In the spring of 2001, as development of the UX6 90nm process reached its climax, NEC Electronics launched the CB-90 Development Promotion Conference to promote the commercialization of new products using 90 nm.

The conference comprised the UX6 device development team, which took charge of developing devices that would employ the UX6 process; the UX6 production working group, which had the task of creating basic specifications for the design rules and libraries; and the GHz ASIC design environment team, which consisted of two working groups focused on setting up the design environment. With clear roles and objectives, the teams set right to work on the tasks they had been assigned (Figure 1).

Until this project, teams of this size and scope had never before been formed for the pursuit of one goal. To resolve the numerous problems facing the project, it was essential to create unified design rules based on a concrete development plan. Selected from among members of the development team and working groups was a person put in charge of process development and the design environment, both of which would be vital to the success of this project. In addition, an elite member of the 1st Custom LSI Division was brought in to head up high-end LSI design. Moreover, even researchers from NEC Silicon Systems Research Laboratory, who at the time were engaged in specialized research on techniques for realization of ultra-high-speed LSI chips in the GHz range, were included in the project. And with this, the stage was finally set for the beginning of what was to become a company-wide project.

The CB-90 development concept

The CB-90 development concept involved simultaneously developing a product and design environment to shorten the development period. In LSI product development of the past, the design environment (manuals, design libraries, tools) was developed first, followed by actual development of the product. This time, however, only a few high-end LSI products were selected for the sake of streamlining the development process, and the development of circuit design and the design environment were carried out simultaneously. This resulted in a dramatic reduction of ballooning design and production costs as well as the time-to-market period.

It was through this development process that an effective method was created for use in the development of high-end LSI products. The design environment used to cultivate the development of the first product was also employed for the next product, and could also be customized. Thus, it was possible to simplify the development of high-end LSI products and reduce both the development period and cost.

The first step in the design stage was to formulate the design rules. This involved the setting of rules for realization of the process that would become the interface between the person in charge of process development and the person in charge of design. The leader of the UX6 device development team, Fumihiro Matsushima of the Technology Foundation Development Division, and the leader of the GHz ASIC design environment team, Toshiyuki Saito, were determined to carry out discussions until everyone involved was in agreement. In fact, it took nearly a year to decide the design rules for CB-90. If the design rules had only been decided on the process development side, it probably wouldn't have taken nearly as much time. However, if that had been the case, problems could have occurred at the design stage, thereby causing product development to be delayed anyway. Haruji Futami, who was transferred from the Advanced Process Division to the Technology Foundation Development Division and therefore understood the arguments being made by both sides, was a key player in the production working group and found himself at the heart of the discussions. If the design rules were left too vague, it would lead to problems later on, and thus there was absolutely no room for compromise.

Focusing on the realization of a GHz ASIC

In comparison with CB-130, which was designed using the 130 nm process, development of CB-90 was aimed at realizing an approximately 20% increase in speed, to more than 1 GHz, integration of a maximum 100 million gates, which is 1.9 times that of the CB-130, and a reduction in power consumption of approximately 40%. Of these three objectives, the development team placed the most emphasis on the actualization of an ASIC that could operate in the GHz range. At the time, the majority of ASICs on the market were at the 100 MHz level and a full-custom IC that could be operated at several GHz was already in existence. In between, however, there was a gap, and this is why NEC Electronics wanted to create a high-efficiency, general-purpose ASIC design platform.

The major challenge faced by the engineers in the development of the GHz ASIC was the construction of the clock, which became a hindrance to efforts being made to increase speed. For tree-structured clock structures in the past, the feasible operating frequency limit of a circuit with more than five million gates was 350 MHz. To go beyond this limit, the development team formulated a clock structure in which the tree structure was integrated with a mesh structure. And by making various other adjustments, high-speed operation at 1 GHz became a reality. In addition, an original clock generation tool capable of semi-automatically generating a clock structure was developed. In this way, the team was able to overcome the greatest barrier that stood in their way and realize an increase in speed. But upon doing so, they found themselves faced with another problem they had never before experienced noise. And with this, the team found itself faced with yet another hurdle.

There were many reasons behind the occurrence of noise. One reason was the influence of inductance that came about as a result of the increase in speed. In comparison with cases in which only electrical resistance and electrical capacitance are considered, some of the effects of inductance include phenomena such as sudden slopes in the rise of signal waveform, fluctuations in delay time and the overshooting or undershooting of a waveform (Figure 2). Although this had been anticipated, the calculation results from the simulator and the value found when the test chip was actually created and operated were inconsistent. An investigation to determine the cause was carried out by repeating various tests, including noise analysis and reexamination of timing. In the end, it turned out that the cause was a simple one. Since the measured frequency had been set rather high, the frequency dependence of wiring resistance was not being dealt with appropriately. The GHz ASIC design environment team, in collaboration with researchers from the NEC Silicon Systems Research Laboratory who were participating in this project, solved this problem by investigating the influence of frequency dependence of resistance on chip performance for the hypothesized 1 GHz clock frequency and then considering countermeasures.

(Frequency dependence is a phenomenon in which, for example, there is an increase in frequency coupled with a significant rise in wiring resistance. In cases in which the high-frequency current is passed through the wiring, frequency dependence occurs when the electrons that flow through the wiring due to the operation of the electromagnetic waves surrounding the wiring become concentrated in the direction of the surface.)

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