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EMMA3SL/L (µPD61310 - µPD61314), EMMA3SL/LP (µPD61315 - µPD61319)




Overview

µPD6131x

EMMA3SL/L(µPD6131x) is an image processing LSI chip that integrates the functions required for receiving digital broadcasting, such as decode functions for digital video, audio signals, and image display, into a single chip.

EMMA3SL/LP(µPD61315-9) is a variation chip of EMMA3SL/L(µPD6131x) with built-in security function to prevent unauthorized reception of paid digital broadcasting. These devices are ideal for STB markets in Easter Europe, Russia, India, and South Africa, where the H.264's SD format is gaining popularity.


Target System

  • H.264 STBs
  • Systems with advanced security features (SL/LP)

Product Specification

Product Specification
On-chip CPU
  • Main CPU:
    • MIPS32® 4KEc® core
    • 440MIPS@288MHz
    • 8 KB instruction cache; 8 KB data cache
Memory Interface
  • DDR2 memory interface
    • 16-bit bus
    • 32 to 128 MB total memory
    • 1.2 GB/s bandwidth
  • Flash ROM interface
    • Up to 64 MB capacity
    • 8-, 16-bit bus
MPEG Transport Stream Processing Engine
  • 2-system parallel/serial selectable stream interface
  • Supports MPEG-compliant transport streams
  • 36 PID filters
  • 32 section filters
MPEG Video Decoder
  • Support Format
    • MPEG2 MP@ML
    • H.264/AVC HP, MP@L3.2
    • VC-1 AP@L1
    • DivX® Home Theatre Profile 3.11, 4.x, 5.x, 6.x
Audio Controller
  • Support Format
    • MPEG-1/2 L1/2, MPEG4 AAC, MPEG4 HE-AAC, DD, DD+, MP3, and WMA
  • SPDIF output
  • Audio PDM output
Graphics and Display Engine
  • 2D Bit BLT
  • Five graphics planes
  • 256-level alpha-blending function
  • 1/4-4x real-time scalar x 2
  • Easy de-interlace function
Video Encoder
  • 4ch Video DAC : CVBS, YC, YPbPr, RGB
  • NTSC/PAL/SECAM
USB2.0 Interface
  • Compliant with EHCI specification
  • High (480 Mbps), full (12 Mbps), and low speeds (1.5 Mbps)
Ethernet Interface
  • Integrated Ethernet MAC conforming to IEEE 802.3/3u/3x
  • Compliant with RMII (10 Mbps/100 Mbps Ethernet) specification
Peripherals
  • Two-channel FUART
  • One-channel UART
  • Two-channel SmartCard interface
  • Two-channel I2C interface
  • Clocked serial interface
  • Two system timers
    • WDT
    • RTC
  • Two-channel IR receiver; IR blaster
Package
  • 389-pin plastic BGA


Block Diagram

Block Diagram



This device is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
This Device can only be sold or distributed to Authorized Buyers.



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