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Products > Digital AV LSI > MPEG Decoder for STB >

EMMA2SE (µPD61140, µPD61141),  EMMA2SE/P (µPD61142)

LSI for Set Top Boxes with Hard Disk Drives


Overview

The highly integrated, single-chip EMMA2SE (µPD6114x) decoders include the function of DVR with dual tuners for digital TV reception. The devices build on the strength of the highly acclaimed EMMA2 series of DVR decoders, adding performance and connectivity enhancements while keeping cost effectiveness in check.
The EMMA2SE/P (µPD61142) decoder offers additional security features for content protection.


Target System

  • Digital video recorders
  • IDTVs
  • Systems with advanced security features (SE/P)

Product Specification

Product Specification
On-chip CPU
  • Main CPU: For application/RTOS/API/BIOS processing
    • On-chip MIPS32® 4KEc® core
    • 284MIPS@186MHz
    • Supports MIPS I™ and MIPS II™ instruction sets
    • Cache size: I-Cache: 8 KB, D-Cache: 8 KB
  • Sub CPU: For decode processing
    • On-chip MIPS32® 4KEm® core
    • 284MIPS@186MHz
    • Cache size: I-Cache: 8 KB, D-Cache: 8 KB, Scratch Pad: 32 KB
Memory Interface
  • RAM Memory I/F
    • Unified RAM Memory I/F: CPU/MPEG decoding/display/graphics, etc.
    • DDR Memory I/F: Supports 16 to 128 MB capacity
  • ROM Memory I/F
    • Supports NOR/NAND Flash ROM
    • Supported maximum capacity: 64 MB (NOR Flash ROM)
MPEG Transport
Stream Processing Engine
  • Hardware processing architecture
  • Stream I/F: Three inputs out of two parallel inputs, two serial inputs, and one playback input
  • MPEG2 TS (Transport Stream)
  • Maximum TS processing rate: 100 Mbps per input, 180 Mbps total (three inputs)
  • 96 general-purpose PID filter
  • 128-section filter
  • Supports HSD (High Speed Data) port output
MPEG Video Decoder
  • Supports MPEG2 MP@ML
Audio Controller
  • Supports MPEG1/MEPG2 layer 1/2
  • Supports DAO (Digital Audio Output) L/R output
  • Supports SPDIF output
Graphics Engine
  • 2D BitBLT
Display
  • Five planes: BG (Background), two Video planes, two OSD planes
  • 256-level alpha-blending function
  • Real-time video scaling (1/4 to 8/1H/V)
  • OSD anti-flicker filter
Video Encoder
  • NTSC/PAL video encoder
  • Supports Closed Caption, WSS, Video ID, VPS, and Teletext
  • 6-channel DAC for simultaneous CVBS, YC, and RGB/YCbDr analog output
  • ITU-R BT.656 digital video output function
Peripherals
  • FUART x 2
  • SmartCard I/F x 2
  • I2C x 2
  • Clocked Serial I/F
  • Timer: Two systems, WDT, RTC
  • IR receiver x 2, IR blaster
  • General PIO
ATA Interface
  • PIO mode, UDMA33, UDMA66
USB2.0 Host Controller
  • Complies with EHCI specifications
  • High speed: 480 Mbps, full speed: 12 Mbps, low speed: 1.5 Mbps
PCI Interface
  • Complies with PCI Rev2.2
  • Clock frequency: 33 MHz, bus width: 32 bits
  • Operates as PCI host or PCI device
Process
  • 0.15 µm CMOS process
  • Power supply: 3.3 V, 2.5 V, 1.5 V



Block Diagram

Block Diagram

Product Lineup

T.B.D



This device is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
This Device can only be sold or distributed to Authorized Buyers.