Beginning of this page
Jump to main content

Please note that JavaScript and style sheet are used in this website,
Due to unadaptability of the style sheet with the browser used in your computer, pages may not look as original.
Even in such a case, however, the contents can be used safely.

Products > Digital AV LSI > MPEG Decoder for STB >

EMMA2LL (µPD61110, µPD61111)

LSI for Low end Digital STB


Overview

The EMMA2LL (µPD6111x) decoders are powerful and highly integrated single-chip solutions for digital set-top boxes (STBs) and iDTVs. Suitable for Free-to-Air and Pay TV applications, these devices employ the second-generation Enhanced Multimedia Architecture (EMMA2) platform for leadership in both cost and performance. Ideal applications include low-end STB/FTA converter and IDTV applications that are moving toward analog switch-off.


Target System

  • Low-end STBs and iDTVs

Product Specification

Product Specification
On-chip CPU
  • Main CPU : Integrated high-performance MIPS32® 4Kc® Core
    • Real-time operating system
    • Application program interface (API)
    • Basic input/output system (BIOS)
    • 200 MIPS at 167 MHz
    • MIPS™ I, MIPS™ II instruction set architectures; subset of MIPS™ III
    • 4 KB instruction and data caches with two types of access
  • Sub CPU : Integrated high-performance MIPS32® 4Km® Core
    • Sub-CPU for MPEG AV and AV-sync decoding inside firmware
    • 200 MIPS at 167 MHz
    • MIPS™ II instruction set architecture
    • 4 KB instruction cache; 4 KB data cache; 8 KB scratch pad
Memory interface
  • Unified memory interface for CPU, MPEG decoder, display, and graphics
    • µPD61110
      • SDR-SDRAM (x 16-bit bus)
      • fMAX= 133 MHz frequency
      • 8, 16, 32, 64, 128 MB
    • µPD61111
      • DDR-SDRAM (x 16-bit bus)
      • fMAX= 133 MHz frequency
      • 16, 32, 64 MB
  • External ROM interface for CPU object code and data
    • Normal, page, and burst ROM
    • NOR, NAND flash ROM
    • 64 MB address space (max.)
    • Two pairs of chip select signals
  • Thirty-two 8- and 16-byte section filters
  • High-speed data output port for IEEE1394 interface
MPEG stream processor
  • NEC processor core for software architecture
  • One parallel port or one serial port for stream input
  • MPEG2 transport stream
  • 100 Mbps (max.)
  • 36 process identifier (PID) filters
    • One video
    • Two audio
    • One processor capacity reservation
    • 32 general
  • Thirty-two 8- and 16-byte section filters
  • High-speed data output port for IEEE1394 interface
MPEG video decoder
  • MPEG2 main profile (MP) at main level (ML) decoding
  • MPEG2 and MPEG1 elementary stream
Audio decoder
  • MIPS32® 4Km® core
    • 200 Dhrystone MIPS at 167 MHz
  • MPEG1 and MPEG2 layer 1 and 2 decoding
  • Pulse-code-modulated L/R audio output
  • Sony™-Phillips™ digital interface format (SPDIF) with IEC60958 digital output (Dolby™ Digital can be passed through to SPDIF)
  • Test tone and mixing
Bit-boundry block transfer
(BIT-BLT) graphics engine
  • Two-dimensional image data transferring
  • RGB 32-to-YCbCr 4:2:2 color conversion for on-screen display
  • Color expansion
Display
  • Four graphics planes
    • One background plane
    • One live video plane
    • Two on-screen display planes (1, 2, 4, 8 bits per pixel + RGB 15, 16, 32)
  • 256-level alpha blending among four planes
  • Real-time scaling for live planes; 1/4 to 4x horizontal and vertical
  • Anti-flicker filter for on-screen display plane
Video encoder
(for analog TV)
  • NTSC, PAL, and SECAM formats
  • Closed captioning, teletext, wide screen scaling (WSS), copy generation management system (CGMS), video ID, and vectors per second (VPS) capabilities
  • Four digital-to-analog converters for conversion of cut before video submission (CBVS), Y/C (luma/chroma), RGB, YCbCr, and YPbPr video output
  • ITU-R BT.656 digital output
Peripherals
  • 16550-compatible UART with two 16-byte FIFOs
  • Two smart card interfaces
  • One I2C port
  • Two system, day, and watchdog timers
  • Four timers supporting input capture timers and output compare timers
  • Clocked serial interface
  • General-purpose I/O
  • Infrared receiver
Process
  • 0.13 µm CMOS process
Power supply voltage
  • VDD: 1.5 V internal and 3.3 V I/O



Block Diagram

Block Diagram


Product Lineup

Order Number Package Package Code
µPD61110GM-100-UEV 216-pin plastic LQFP (24 x 24 mm) P216GM-40-UEV
µPD61111GM-100-UEV 216-pin plastic LQFP (24 x 24 mm) P216GM-40-UEV



This device is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
This Device can only be sold or distributed to Authorized Buyers.



Related Information