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Our R&D


R&D at NEC Electronics

NEC Electronics is committed to contributing to society through research and development that deliver some of the world’s most advanced semiconductors. Cooperating with NEC System Devices Research Laboratories and other members of the NEC Group, NEC Electronics has achieved outstanding results in numerous fields, reflecting a broad R&D focus that ranges from innovations for next-generation process technologies to the development of applied technologies.
These achievements have been announced at forums such as the IEDM, the VLSI Symposium, and the ISSCC, and published in industry journals, thereby contributing to the technological evolution of the semiconductor industry.


Recent Technological Trends

The increasingly rapid technological advances of recent years have brought the IC industry to the point where current architectures are approaching their technological limits, posing a threat to further performance gains. Meanwhile, markets require devices that are faster, smaller, cheaper, and more power efficient – qualities that are difficult to achieve at the same time.
These requirements can be met only through the synergistic integration of new technologies in every aspect of IC production, from device design and deep-submicron fabrication through packaging. As an integrated device manufacturer, NEC Electronics has a competitive edge in its ability to meet market requirements by synergistically leveraging its expertise and cutting-edge technologies at every stage in the IC production process.

Following is an introduction to process technology and packaging, two areas where the results of R&D have been especially notable.


Process Technology

Device Miniaturization

In addition to enhancing the performance of ICs, miniaturization reduces chip sizes, thus driving down both the dimensions and the cost of electronics products. It also reduces electric resistance, for lower power consumption. For these reasons, device miniaturization has been an important focus of research and development.

However, building complex circuits on wafers at nanometer scale and ensuring their proper operation requires the integration of many new and very advanced technologies, such as transistors with modified architectures and special design techniques.

At NEC Electronics, the 55nm node will be based on a miniaturized version of the design rule for the 65nm node. It will feature reduced power consumption and performance comparable to that expected for 45nm process technology. This very deep-submicron processing is enabled by new immersion exposure manufacturing equipment.

For the 45nm node, NEC Electronics, Toshiba, and Sony have jointly developed a high-yield mass production platform that incorporates a number of fundamental advances. For the 32nm node, NEC Electronics and NEC have built on the results of basic research by the semiconductor MIRAI project, developing novel density-modulated low-k layer technology that enables the world’s first multilayer interconnect for 32nm ICs.

NEC Electronics is an active participant in industry research initiatives and is also committed to the development of the proprietary technologies needed to enable next-generation devices.


Advanced Process Technology Roadmap

Low Power Consumption

Greater energy efficiency is an advantage for every type of electronic device, including of course mobile devices. Efficient energy consumption enables higher performance, and also contributes to protection of the environment. For these reasons, techniques to reduce the power consumption of ICs are a major focus in the development of new devices.
NEC Electronics has developed power-saving technology that delivers the required performance while reduces standby power consumption by up to 90%. This revolutionary technology is expected to be become available at the 55nm node.


Packaging Technology

The quest for smaller form factors, higher performance, and more functionality is a common theme in the development of every type of electronics device, from portable and consumer electronics devices to PCs and network servers. To help meet these requirements, NEC Electronics has introduced many packaging innovations, including higher pin counts, smaller footprints, and higher densities (allowing more chips to be mounted per unit of surface area on device boards).

One of these advances is a stacked memory packaging technology that allows 8 memory chips and 1 controller chip to be delivered in a single compact package. Developed jointly by NEC Electronics, Elpida Memory and Oki Electric, with support from the New Energy and Industrial Technology Development Organization (NEDO), this technology allows mobile devices to be equipped with as much memory as a high-performance server. This will facilitate the development of mobile devices capable of complex functions such as high-definition video playback and high-speed 3D game graphics. The new package uses NEC Electronics' advanced SMAFTITM SiP packing technology and features novel through-chip polysilicon electrodes, to achieve an ultra-dense 50µm pitch in an extremely advanced 3D memory package.


Fig. 2 Stacked memory packaging technology
Fig. 2 Stacked memory packaging technology