V5.5(CB9, CB10)
<How to obtain documents>
These documents can be obtained from the following distributors and NEC Electronics sales offices.
OPENCAD V5.5x (CB9VM/VX, CB10_VX, CB10VXLIO)
|
Document Name
|
Document No.
|
|
OPENCAD
|
Wave Editor
|
A14954E
|
|
Design Rule Check STADRC
|
A14967E
|
|
Constraint Description For Signal Integrity
|
A15882E
|
|
OPC_VSHELL
|
A17226E
|
|
Design Rule Check GateDRC
|
A16216E
|
|
Logic Simulation
|
Simulator (VCS, NC-Verilog, Verilog-XL, ModelSim, V.sim)
|
A16885E
|
|
Static Timing Analyzer
|
PrimeTime Interface
|
A14961E
|
|
Static Timing Analyzer Operation (Tiara)
|
A15858E
|
|
Static Timing Analyzer Operation (PrimeTime/TimeCraft)
|
A17664E
|
|
Static Timing Analyzer Tiara
|
A16210E
|
|
Schematic Editor
|
Vdraw
|
A14953E
|
|
Logic Synthesis
|
Design Compiler Interface
|
A17319E
|
|
Fault Simuration
|
C.FGRADE
|
A15061E
|
|
Formal Verification
|
Formality Interface
|
A14968E
|
|
Conformal-LEC Interface
|
A16234E
|
|
Design For Test
|
DFT Compiler/TetraMAX
|
A14964E
|
|
NEC_BIST, NEC_TESTBUS, NEC_SCAN/SCAN2, NEC_BSCAN/BSCAN2
|
A15168E
|
|
TESTACT, NEC_SCAN2
|
A16437E
|
|
Manual TESTBUS Design Guideline
|
A17104E
|
|
Tester Interface
|
Test Vector
|
A14966E
|
|
