Documentation List

These documents can be obtained from the following distributors and NEC Electronics sales representatives.

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Note that documents distributed herein may be preliminary versions, even if not labeled as such.

Documentation List
CB-40	Design Manual Block Library OPENCAD
CB-55	Design Manual Block Library OPENCAD
CB-90	Design Manual Block Library Data Sheet OPENCAD
CB-130	Design Manual Block Library Memory Macro OPENCAD
CB-12	Design Manual Block Library Memory Macro Analog Macro Common Analog Macro OPENCAD

CB-40

Document Name Japanese English Design Manual L Type Product Data A19747J A19747E LD Type Product Data A19915J A19915E Block Library L Type (WIDE 1.1V) - A19705E Memory Macro L Type A19699J A19699E LD Type A20062J A20062E Static Timing Analyzer Static Timing Analyzer Operation (PrimeTime/TimeCraft) A17664J A17664E Formal Verification Formality Interface A19783J - Conformal-LEC Interface A19832J - Design For Test Manual TESTBUS Design Guideline A17104J A17104E

CB-55

Document Name Japanese English Design Manual L Type Product Data A19134J A19134E Block Library L Type (WIDE 1.2V) - A19128E Memory Macro L Type A19481J A19481E Static Timing Analyzer Static Timing Analyzer Operation (PrimeTime/TimeCraft) A17664J A17664E Formal Verification Formality Interface A19783J - Conformal-LEC Interface A19832J - Design For Test Manual TESTBUS Design Guideline A17104J A17104E

CB-90

Document Name Japanese English Design Manual M Type Product Data A17900J A17900E M Type Circuit Design A18903J A18903E L Type Product Data A17901J A17901E Block Library M Type (WIDE 1.0V) - A17270E M Type (NARROW 1.0V) - A17355E L Type (WIDE 1.2V) - A17474E Memory Macro M Type A19049J A19049E L Type A19050J A19050E Data Sheet A/D Converter Core - D/A Converter Core - OPENCAD Wave Editor A14954L A14954E Design Rule Check STADRC A14967J A14967E Constraint Description For Signal Integrity A15882J A15882E Utility A17140J A17140E OPC_VSHELL A17226J A17226E Design Rule Check GateDRC A16216J A16216E Logic Simulation Simulator (VCS, NC-Verilog, Verilog-XL, ModelSim, V.sim) A16885J A16885E Static Timing Analyzer PrimeTime Interface A14961J A14961E Static Timing Analyzer Operation (Tiara) A15858J A15858E Static Timing Analyzer Operation (PrimeTime/TimeCraft) A17664J A17664E Static Timing Analyzer Tiara A16210J A16210E Static Timing Analyzer OPC_Tiara A18171J - Logic Synthesis Design Compiler Interface A17319J A17319E Formal Verification Formality Interface A14968J A14968E Conformal-LEC Interface A16234J A16234E Fault Simulation C.FGRADE A15061J A15061E Design For Test DFT Compiler/TetraMAX A14964J A14964E TESTACT Operation Manual Circuit Design (for L Type) A17891J - Manual TESTBUS Design Guideline A17104J A17104E TESTACT Operation Manual A17464J A17464E Tester Interface Test Vector A14966J A14966E

CB-130

Document Name Japanese English Design Manual M Type Product Data A16212J A16212E Block Library M Type (CMOS1.2V) - A16215E Memory Macro M Type A16399J A16399E OPENCAD Wave Editor A14954J A14954E Design Rule Check STADRC A14967J A14967E Constraint Description For Signal Integrity A15882J A15882E Utility A17140J A17140E OPC_VSHELL A17226J A17226E Design Rule Check GateDRC A16216J A16216E Logic Simulation Simulator (VCS, NC-Verilog, Verilog-XL, ModelSim, V.sim) A16885J A16885E Static Timing Analyzer PrimeTime Interface A14961J A14961E Static Timing Analyzer Operation (Tiara) A15858J A15858E Static Timing Analyzer Operation (PrimeTime/TimeCraft) A17664J A17664E Static Timing Analyzer Tiara A16210J A16210E Static Timing Analyzer OPC_Tiara A18171J - Logic Synthesis Design Compiler Interface A17319J A17319E Formal Verification Formality Interface A14968J A14968E Conformal-LEC Interface A16234J A16234E Fault Simulation C.FGRADE A15061J A15061E Design For Test DFT Compiler/TetraMAX A14964J A14964E RobustSCAN A16728J A16728E TESTACT Operation Manual Circuit Design A17891J - Manual TESTBUS Design Guideline A17104J A17104E TESTACT Operation Manual A17464J A17464E Tester Interface Test Vector A14966J A14966E

CB-12

Document Name Japanese English Design Manual L/M Type Product Data A14937J A14937E L/M Type Circuit Design A15135J A15135E Block Library L/M Type (CMOS1.5V) - A15353E L/M Type (TTL1.5V) - A15354E Memory Macro L Type A16458J A16458E M Type A16730J A16730E H Type A15105J A15105E Analog Macro Common Cell-Based IC with PLL A15508J A15508E Cell-Based IC with DAC Circuit Design A15698J A15698E Cell-Based IC with ADC Circuit Design A16347J A16347E OPENCAD Wave Editor A14954J A14954E Design Rule Check STADRC A14967J A14967E Constraint Description For Signal Integrity A15882J A15882E OPC_VSHELL A17226J A17226E Design Rule Check GateDRC A16216J A16216E Logic Simulation Simulator (VCS, NC-Verilog, Verilog-XL, ModelSim, V.sim) A16885J A16885E Static Timing Analyzer PrimeTime Interface A14961J A14961E Static Timing Analyzer Operation (Tiara) A15858J A15858E Static Timing Analyzer Operation (PrimeTime/TimeCraft) A17664J A17664E Static Timing Analyzer Tiara A16210J A16210E Static Timing Analyzer OPC_Tiara A18171J - Schematic Editor Vdraw A14953J A14953E Logic Synthesis Design Compiler Interface A17319J A17319E Formal Verification Formality Interface A14968J A14968E Conformal-LEC Interface A16234J A16234E Fault Simulation C.FGRADE A15061J A15061E Design For Test DFT Compiler/TetraMAX A14964J A14964E RobustSCAN A16728J A16728E TESTACT Operation Manual Circuit Design A17891J - Manual TESTBUS Design Guideline A17104J A17104E TESTACT Operation Manual A17464J A17464E Tester Interface Test Vector A14966J A14966E