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Test Solutions
In recent years, the trend toward LSIs with ever higher levels of speed, functionality, and integration, made possible by ongoing miniaturization of fabrication processes, has made it more important than ever to ensure high test quality.
NEC Electronics has introduced several test methodologies that raise LSI quality to meet today's needs.
Scan delay test
This delay test method uses the configuration of the scan test circuitry. The capture rate during scan mode is accelerated and delay tests are performed along paths between flip-flops where a same-phase clock is supplied.
Pattern compression
With the trends toward higher circuit integration and an expansion of test items, the number of patterns have increased, which tends to lengthen the testing time. To overcome this problem and shorten testing times, various pattern compression technologies have been introduced.
To implement pattern compression, pattern supply circuits and pattern compression circuits are added to the scan circuit in order to split the scan chain and thereby reduce the pattern volume and the number of test cycles.
High-speed SRAM BIST
NEC Electronics provides tools that supply a clock signal to drive BIST (Built-In Self Test), thereby speeding up SRAM testing.
