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Solutions for Lower Power Consumption during Active and Standby Modes
In LSI development, low power consumption is always a large part of the needs expressed by customers.
Recently, low power consumption has become essential not only for system development but also for environmental reasons, and in fact low power consumption has become an ever larger part of the needs expressed by customers.
NEC Electronics has pursued this issue via various approaches, as it seeks to provide cell-based ICs that meet today's challenging needs for lower power consumption during active and standby modes.
Countermeasures starting at early development stages
To achieve lower power consumption during active and standby modes, NEC Electronics has gone beyond applying technologies one at a time, and instead seeks to maximize power saving effects by pursuing low power consumption as a design methodology starting from the logic design stage.
Clock gating
With the recent increase in functions implemented in LSIs, in some cases there are many circuits which do not operate, depending on the customer's system status.
Supplying clock signals to these non-operational circuits is a waste of power.
By controlling (gating) the clock signals supplied to such circuits, power consumption can be reduced along the clock lines and other gated circuits.
Use of multi-Vt cells and specialized power-saving cells
One way to reduce standby power consumption is to use multi-Vt cells. Ordinarily, low Vt cells that operate at high speeds are used during layout, but these are replaced by high Vt cells for blocks in circuits or paths that do not require high-speed operation, which can reduce standby power consumption. Using specialized power-saving cells can be an effective way to reduce operational power consumption. These specialized power-saving cells not only reduce the drive capacity but are also featured in blocks for low power consumption (NEC Electronics' proprietary technology) that have a shorter gate width than other blocks. After layout is completed, blocks along paths that are free of timing errors are replaced by these specialized power-saving cells to reduce operational power consumption.
These multi-Vt cells and specialized power-saving cells match their artwork shapes and pin position to blocks having the same functions, so they can be used as replacements without having to redo the wiring layout.
Consequently, power consumption can be cut without lengthening the layout turnaround time.
