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Development Flow and Layout Design Technology
Development flow
With recent advances in miniaturization technologies, the development turnaround time for larger-scale LSIs has become longer than ever.
NEC Electronics works with customers starting from the early stages of product development and on through layout design and other stages, providing a support system and development tools to facilitate progress.
By cooperating with customers from the early stages onward, NEC Electronics helps shorten the customer's turnaround time for each development iteration by checking for problems in timing convergence, placement and routing, etc., which helps raise the quality of development. This teamwork also helps to make LSI development period estimations more accurate, enabling customers to stay on schedule in their system development projects.
Layout design technology for shorter turnaround time and faster circuits
NEC Electronics is trying out various methodologies for raising the efficiency of layout processes.
First, they provide a development flow in which provisional netlists are used at the early development stages to draft a layout design. This helps reduce the number of revisions that have to be made at subsequent processes and thereby shortens development turnaround time.
Using NEC Electronics' proprietary timing optimization tool, timing convergence and SI (Signal Integrity) verification of the chip layout can be performed more quickly, which makes the layout process more efficient for high-speed circuits and other circuits with challenging timing requirements. Also, NEC Electronics provides specialized cells for circuit revision, which helps to shorten the turnaround time for layout following the circuit revisions.
