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Solutions for Development of Cutting-edge LSIs


As LSI development enters the 90 nm or 55 nm era, both technical needs and implementation methods have become more challenging.
NEC Electronics is working hard to bring about new technologies and approaches that are able to meet these challenges.


UltimateLowPower™ design technology

Standby leakage is a growing problem as fabrication processes become further miniaturized. To maintain steady performance while lowering the power supply voltage, both the Vth (threshold voltage) and gate insulation layer must be reduced.
UltimateLowPower not only reduces operational power consumption, it works better than ever to eliminate power leakage during standby mode. NEC Electronics provides this technology to customers developing their own LSIs, so these customers do not have to create any special designs.


UltimateLowPower design technology

Effectiveness of UltimateLowPower™ in reducing power consumption

NEC Electronics has been able to reduce chip-level power leakage by one-third (vs. its previous models) by using power supply controllers (delay monitors and voltage regulators) which automatically control the board bias. In addition, the company has developed transistor technology that features more bias-sensitive circuit design technology and uses high-K gate oxidation films, thereby cutting the chip's power consumption to 1/30th the previous level.
Customers do not have to create any special designs to accommodate this board bias control. The power supply controller is provided by NEC Electronics to customers who are developing their own LSIs.


Effectiveness of UltimateLowPower in reducing power consumption


Package integrated design environment

NEC Electronics has developed a chip package integrated design environment that enables virtual verifications of electrical characteristics after packaging to be performed when creating LSI specifications. This means reworking will occur less often during LSI development.
Specifically, a virtual LSI model that integrates the chip and package is created, and a simulation is then performed to verify electrical characteristics in advance.
Since both the chip design and package design can be verified in advance at an early development stage, the LSI development lead time is shortened, enabling more rapid development of the customer's products and a faster time to market for customer systems.


Package integrated design environment


UltimateLowPower is a trademark of NEC Electronics Corporation.
GENISSNX is a trademark of NEC Informatec Systems,Ltd.