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Products > ASIC > Cell-Based IC > IP Core >

eDRAM


Embedded DRAM Macro Lineup

Contact NEC Electronics regarding support.


UX6LD (90 nm, 1.2 V)


Memory Size Configuration
(word x bit)*1 		Random Access
Cycle (tRCK)*2
  		VDD Tj
4 Mb 32 Kw x 128 b 100 MHz 1.2 V ± 0.1 V 0 °C to 105 °C
8 Mb 64 Kw x 128 b 100 MHz 1.2 V ± 0.1 V 0 °C to 105 °C
12 Mb 48 Kw x 256 b 83 MHz 1.2 V ± 0.1 V 0 °C to 105 °C

Note(*)

  1. Custom configurations are available upon request.
  2. The random access cycle (tRCK) is under the worst case condition. VDD=1.1V, Tj=105(°C) and worst case process corner.

UX5D (130 nm, 1.2 V)


Memory Size Configuration
(word x bit)*1 		Random Access
Cycle (tRCK)*2
  		VDD Tj
9 Mb 64 Kw x 144 b 200 MHz 1.2 V ± 0.1 V 0 °C to 105 °C
8 Mb 64 Kw x 128 b 200 MHz 1.2 V ± 0.1 V 0 °C to 105 °C
8 Mb 128 Kw x 64 b 200 MHz 1.2 V ± 0.1 V 0 °C to 105 °C
2.25 Mb 16 Kw x 144 b 200 MHz 1.2 V ± 0.1 V 0 °C to 105 °C

Note(*)

  1. Custom configurations are available upon request.
  2. The random access cycle (tRCK) is under the worst case condition. VDD=1.1V, Tj=105(°C) and worst case process corner.

UX4D (150 nm, 1.5 V)


Memory Size Configuration
(word x bit)*1 		Random Access
Cycle (tRCK)*2
  		VDD Tj
8 Mb 64 Kw x 128 b 143 MHz 1.5 V ± 0.1 V 0 °C to 105 °C
8 Mb 128 Kw x 64 b 100 MHz 1.5 V ± 0.1 V 0 °C to 105 °C
4 Mb 64 Kw x 64 b 100 MHz 1.5 V ± 0.1 V 0 °C to 105 °C

Note(*)

  1. Custom configurations are available upon request.
  2. The random access cycle (tRCK) is under the worst case condition. VDD=1.4V, Tj=105(°C) and worst case process corner.