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Products > ASIC > Cell-Based IC > IP Core > Analog Core >

PLL/VCO/SSCG Core


Features and Introduction

A phase locked loop, or PLL, is a type of oscillator used, for example, in the generation of ASIC system clocks. PLLs are broadly divided into whether a definition of the phase relationship between PLL input and output is required or not required. Development of spread-spectrum clock generators (SSCGs) for reducing electromagnetic interference (EMI) levels is also progressing.


Topic


Lineup

Type MHz
(min.) 		MHz
(max.) 		CB-9 CB-10 CB-12 CB-130 CB-90
SkewControl 140 240 P        
133 266   P (2.5 V)      
200 266   P (2.5 V)      
150 267 P        
220 280 P        
160 320       O (M: 1.2 V)  
200 400     O (M: 1.5 V)   O (M: 1.0 V)
300 540       O (M: 1.2 V)  
650 1340         O (M: 1.0 V)
Multiplying 25 50     O
(M: 0.9-1.65 V) 		   
35 70     O (M: 1.5 V)    
20 80   P (2.5 V)      
45 100     O
(M: 0.9-1.65 V) 		   
70 120 O   O (M: 1.5 V)    
75 150       O (M: 3.3 V)  
77 154 P        
120 170 O        
90 180       O (M: 1.2 V)  
100 200     O (M: 1.5 V)    
50 230 P        
60 250     O (M: 1.5 V)   O (M: 1.0 V)
160 250 O        
60 270   P (2.5 V)      
160 320       O (M: 1.2 V)  
170 340         O (L: 1.2 V)
200 400         O (M: 1.0 V)
250 400     O (M: 1.5 V)    
300 600       O (M: 1.2 V)  
SSCG 24 48   O (2.5 V)      
48 100     O (M: 1.5 V)    
100 200     O (M: 1.5 V)    
160 320       O (M: 1.2 V)  
200 400         O (M: 1.0 V)
400 800         O (M: 1.0 V)
Multi Phase Output 400 800     O (M: 1.5 V)    
600 1200         O (M: 1.0 V)

O : Officially released,   P : Provisionally released,   ↓ : Another type core available,
* : Contact NEC Electronics regarding support.